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Freescale Semiconductor Product Brief
9S12XDFAMPP Rev. 2.14, 7-Nov-2005
MC9S12XD Family
16-bit Microprocessor Family (covers MC9S12XD64 through MC9S12XDP512 and MC3S12XDT256/MC3S12XDG128)
Introduction
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Targeted at automotive multiplexing applications, the MC9S12XD Family will deliver 32-bit performance with all the advantages and efficiencies of a 16-bit MCU. The S12X is designed to retain the low cost, low power consumption, excellent EMC performance and code-size efficiency advantages enjoyed by users of Freescale's previous 16-bit MC9S12 MCU family. Based around an enhanced S12 core, the MC9S12XD Family will deliver two to five times the performance of a 25 MHz S12 whilst retaining a high degree of pin and code compatibility with the original S12D - family. The MC9S12XD Family features the performance boosting XGATE co-processor. The XGATE, which is programmable in "C" language, has an instruction set which is optimized for data movement, logic and bit manipulation instructions. It runs at twice the bus frequency of the S12X and off-loads the CPU by providing high speed data transfer (and data processing) between any peripheral module, RAM and I/O ports. This is particularly useful in applications such as automotive gateways where there are multiple busses carrying heavy data traffic which would otherwise exert a heavy interrupt/processing load on the CPU.
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
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Features
The MC9S12XD Family will feature an enhanced MSCAN module which, when used in conjunction with XGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retains backwards compatibility with the MSCAN module featured on previous S12 products. Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotive spec SG-Flash with additional integrated EEPROM. In addition to the rich S12 peripheral set, the MC9S12XD Family will feature more RAM, extra A/D channels, new timer features and additional LIN-compatible SCI ports compared with the original S12 DFamily. The MC9S12XD Family also features a new flexible interrupt handler which allows multilevel nested interrupts. The MC9S12XD Family has full 16-bit data paths throughout. The non-multiplexed expanded bus interface available on the 144-pin versions allows an easy interface to external memories. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. System power consumption is further improved with the new "fast exit from STOP mode" feature and an ultra low power wakeup timer. In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt capability allowing wakeup from STOP or WAIT mode. The MC9S12XD Family will be available in 144-pin LQFP (with optional external bus), 112-pin, and 80-pin options.
Features
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* * Upward compatible with MC9S12 instruction set Enhanced indexed addressing Additional (superset) instructions to improve 32-bit calculations and semaphore handling Access large data segments independent of PPAGE Eight levels of nested interrupt Flexible assignment of interrupt sources to each interrupt level. One non-maskable high priority interrupt (XIRQ) Wakeup interrupt inputs - IRQ and non-maskable XIRQ
Features of the MC9S12XD Family are listed here. Please see Table 1 for memory options and Table 2 for the peripheral features that are available on the different family members.
16-bit CPU12X
* * *
Enhanced Interrupt Module
* * *
MC9S12XD Family, Rev. 2.14 2 Freescale Semiconductor
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Features
* * * XGATE * * * * * * *
Programmable, high performance I/O co-processor module -- up to 80 MIPS RISC performance Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states Performs logical, shifts, arithmetic, and bit operations on data Enables FullCAN capability when used in conjunction with MSCAN module Full LIN master or slave capability when used in conjunction with the six integrated LIN SCI modules Can interrupt the HCS12X CPU signalling transfer completion Triggers from any hardware module as well as from the CPU possible 64K, 128K, 256K, 384K and 512K byte Flash 128K and 256K ROM Flash General Features - Erase sector size 1024 bytes - Automated program and erase algorithm - Fast sector erase and word program operation - 2-stage command pipeline for faster multi-word program times - Sector erase abort feature for critical interrupt response - Protection scheme to prevent accidental program or erase - Security option to prevent unauthorized access - Code integrity check using built-in data compression - Sense-amp margin level setting for reads 1K, 2K, 4K byte EEPROM - Small erase sector (4 bytes) - Automated program and erase algorithm - Fast sector erase and word program operation - 2-stage command pipeline for faster multi-word program times - Sector erase abort feature for critical interrupt response - Protection scheme to prevent accidental program or erase 4K, 8K, 12K, 14K, 16K, 20K, 32K Byte RAM
Memory Options
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*
*
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 3
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Features
* * * Oscillator (OSC_LCP)
Loop control Pierce oscillator using a 0.5 MHz to 16 MHz crystal Option for full-swing Pierce without internal feedback resistor using a 0.5 MHz to 40 MHz crystal Current gain control on amplitude output - Signal with low harmonic distortion - Low power - Good noise immunity - Eliminates need for external current limiting resistor Transconductance sized for optimum start-up margin for typical crystals Clock monitor Phase-locked-loop clock frequency multiplier - Reference divider - Automatic bandwidth control mode for low-jitter operation - Automatic frequency lock detector Fast wakeup from STOP in self clock mode for power saving and immediate program execution Computer operating properly (COP) watchdog with optional safety window to initialize timeout counter Real time interrupt for task scheduling purposes or cyclic wakeup from low power modes
* * *
Clock and Reset Generator (CRG)
* * *
* System reset generation www..com * * Non-Multiplexed External Bus (144 Pin package only) * * * 16 bit data
Support for external WAIT input or internal wait cycles to adapt MCU speed to peripheral speed requirements Up to four chip select outputs to select 16K, 1M, 2M and 4M byte address spaces Supports glue-less interface to popular asynchronous RAMs and Flash devices External address space 4M byte for data and program space
MC9S12XD Family, Rev. 2.14 4 Freescale Semiconductor
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Features
* * * * Analog-to-Digital Converter (ATD) * * * * * * * * * Enhanced Capture Timer (ECT) * *
Up to two independent ADC converters (see Table 2) 8-bit or 10-bit resolution Multiplexer for 16 analog input channels 7 s, 10-bit single conversion time Programmable sample time Left/right, signed/unsigned result data Continuous conversion mode Multiple channel scans External and internal conversion trigger capability Pins can also be used as digital I/O Eight 16-bit channels for input capture or output compare One 16-bit free-running counter with 8-bit precision prescaler One 16-bit modulus down counter with 8-bit precision prescaler Four 8-bit or two 16-bit pulse accumulators Four channels have enhanced input capture capabilities: - Delay counter for noise immunity - 16-bit capture buffer - 8-bit pulse accumulator buffer Four channel x 24-bit modulus down-count timers - Timeout interrupt - Timeout peripheral trigger Start of timers can be aligned Eight channel x 8-bit or four channel x 16-bit pulse width modulator Programmable period and duty cycle per channel Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies
Periodic Interrupt Timer (PIT)
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* * * * *
*
Pulse Width Modulator (PWM)
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 5
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Features
* *
Up to five MSCAN modules (see Table 2) CAN 2.0 A, B software compatible - Standard and extended data frames - 0-8 bytes data length - Programmable bit rate up to 1 Mbps Five receive buffers with FIFO storage scheme Three transmit buffers with internal prioritization Flexible identifier acceptance filter programmable as: - 2 x 32-bit - 4 x 16-bit - 8 x 8-bit Wakeup with integrated low-pass filter option Loop back for self test Listen-only mode to monitor CAN bus Bus-off recovery by software intervention or automatically 16-bit time stamp of transmitted/received messages FullCAN capability when used in conjunction with XGATE Up to three SPI modules (see Table 2) Full-duplex or single-wire bidirectional Double-buffered transmit and receive MSB-first or LSB-first shifting Serial clock phase and polarity options Up to six SCI modules (see Table 2) Full-duplex or single wire operation Standard mark/space non-return-to-zero (NRZ) format Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths 13-bit baud rate selection Programmable character length Programmable polarity for transmitter and receiver Receive wakeup on active edge Break detect and transmit collision detect supporting LIN
* * Multi-scalable Controller Area Networks (MSCAN) *
* * * * * * * * Serial Peripheral Interface (SPI) * * * * * * * Serial Communication Interfaces (SCI) * * * * *
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MC9S12XD Family, Rev. 2.14 6 Freescale Semiconductor
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Features
* * * * * * Inter IC Module (IIC) * * * * * * * * Background Debug (BDM)
Up to two IIC modules (see Table 2) Compatible with I2C Bus standard Multi-master operation Software programmable for one of 256 different serial clock frequencies Software selectable acknowledge bit Interrupt driven byte-by-byte data transfer Arbitration lost interrupt with automatic mode switching from master to slave Calling address identification interrupt Start and stop signal generation/detection Repeated start signal generation Acknowledge bit generation/detection Bus busy detection supports 400 Kbps Background debug controller (BDM) with single-wire interface - Non-intrusive memory access commands - Supports in-circuit programming of on-chip non-volatile memory - Supports security
* Four comparators A, B, C and D www..com - Each can monitor CPU or XGATE busses - Debugger (XDBG) * * * System Protection * * * Input/Output * * - - A and C compares 23-bit address bus and 16-bit data bus with mask register B and D compares 23-bit address bus only Three modes: simple address/data match, inside address range or outside address range
64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every access Tag-type or force-type hardware breakpoint requests Power-on reset (POR) illegal address detection with reset Low-voltage detection with interrupt or reset up to 117 general-purpose input/output (I/O) pins depending on the package option and 2 input-only pins Hysteresis and configurable pullup/pulldown device on all input pins Configurable drive strength on all output pins
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 7
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Features
* Package Options * * * *
144-pin low-profile quad flat-pack (LQFP) 112-pin low-profile quad flat-pack (LQFP) 80-pin quad flat-pack (QFP) Ambient temperature range -40C to 125C Temperature options: - -40C to 85C - -40C to 105C - -40C to 125C Supply voltage 3.15V to 5.5V Internal voltage regulator providing 2.5 V logic supply - 40 MHz maximum CPU bus frequency in single chip mode - 80 MHz maximum XGATE bus frequency
Operating Conditions * *
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MC9S12XD Family, Rev. 2.14 8 Freescale Semiconductor
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MC9S12XD Family Block Diagram
MC9S12XD Family Block Diagram
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MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 9
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MC9S12XD Family Block Diagram
512K/384K/256k/128K/64K Byte Flash 32K/20K/16K/14K/12K/8K/4K Byte RAM 4K/2K/1K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET TEST PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 VRH VRL VDDA VSSA VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7
ATD0
ATD1
Voltage Regulator
Single-wire Background Debug Module Clock and Reset Generation Module
CPU12X
Enhanced Multilevel Interrupt Module Periodic Interrupt COP Watchdog Clock Monitor Breakpoints
PLL
XGATE
Peripheral Co-Processor
ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 EWAIT ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 UDS ADDR0 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
CAN2 CAN3 CAN4 SCI2 IIC1 IIC0
SCI3 Non-Multiplexed External Bus Interface (EBI)
VDD1,2 VSS1,2
RXD TXD
Digital Supply 2.5V
PLL Supply 2.5V
VDDPLL VSSPLL
Analog Supply 3-5V
VDDA VSSA
PWM
I/O Supply 3-5V
VDDX1,2 VSSX1,2
Voltage Regulator 3-5V
VDDR1,2 VSSR1,2
SPI1
RXD TXD RXD TXD
SCI4 SCI5
SPI2
SDA SCL SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS
KWJ0 KWJ1 KWJ2 KWJ4 KWJ5 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7
PTM
CAN1
DDRM
Timer 4 channel 16 bit with Prescaler for internal timebases
CAN0
Module to Port Routing
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DDRA DDRB DDRC DDRD PTA PTB PTC PTD
XIRQ IRQ R/W/WE LSTRB/LDS/EROMCTL ECLK MODA/RE/TAGLO MODB/TAGHI ECLKX2/XCLKS IQSTAT0 IQSTAT1 IQSTAT2 IQSTAT3 8 Bit PPAGE ACC0 Allows 4MByte ACC1 Program space ACC2 ROMCTL/EWAIT
DDRE
PTE
Enhanced Capture Timer
SCI0 SCI1 SPI0
MISO MOSI SCK SS RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXD TXD
PJ0 CS3 PJ1 PJ2 CS1 PJ4 CS0 PJ5 CS2 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7
DDRP
DDRH
MC9S12XD Family, Rev. 2.14 10 Freescale Semiconductor
PTH
PTP
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Signals shown in Bold-Italics are neither available on the 112 Pin nor on the 80 Pin Package Option Signals shown in Bold are not available on the 80 Pin Package
DDRS DDRJ
PTJ
PTS
AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD
DDRAD0 & AD0
DDRT
PTT
DDRAD1 & AD1
DDRK
PTK
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MC9S12XD Family Block Diagram
Table 1. Package and Memory Options of MC9S12XD Family Members
Device 9S12XDP512 112 LQFP 144 LQFP 9S12XDT512 112 LQFP 80 QFP 144 LQFP 9S12XDT384 112 LQFP 80 QFP 144 LQFP 9S12XDQ256 112 LQFP 80 QFP 16K 144 LQFP 9S12XDT256 112 LQFP 256K 80 QFP www..com 144 LQFP 9S12XD256 112 LQFP 80 QFP 144 LQFP 3S12XDT256 112 LQFP 80 QFP 112 LQFP 9S12XDG128 80 QFP 12K 112 LQFP 3S12XDG128 80 QFP 112 LQFP 9S12XD128 80 QFP 9S12XD64 NOTES:
1. No EEPROM is available on ROM versions. 128K
(1)
Package 144 LQFP
Flash
RAM 32K
EEPROM
ROM
512K 20K
384K
20K
4K
14K
16K
(1)
256K
128K
2K
128K
8K 4K
2K
80 QFP
64K
1K
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 11
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MC9S12XD Family Block Diagram
Table 2. Peripheral Options of MC9S12XD Family Members
Device
9S12XDP512
Package 144LQFP 112LQFP 144LQFP
XGATE
CAN 5 5 3 3 3 3 3 3 4 4
SCI 6 4 6 4 2 4 4 2 4 4 2 4 4 2
SPI 3 3 3 3 2 3 3 2 3 3 2 3 3 2
IIC 2 1 1 1 1 1 1 1 1 1 1 1 1 1
ECT 8 8 8 8 8 8 8 8 8 8 8 8 8 8
PIT 4 4 4 4 4 4 4 4 4 4 4 4 4 4
A/D 2/24 2/16 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 2/24 2/16 1/8 1/16(2) 1/8 1/16(2) 1/8 1/16(2) 1/8 1/8
I/O 119 91 119 91 59 119 91 59 119 91 59 119 91 59 119 91 59 119 91 59 91 59 91 59 91 59 59
9S12XDT512
112LQFP 80QFP 144LQFP
9S12XDT384
112LQFP 80QFP 144LQFP
9S12XDQ256
112LQFP
yes
80QFP 144LQFP
9S12XDT256
4 3 3 3
112LQFP 80QFP 144LQFP
1 4 2 1 8 www..com4 1 1 3 3 3 2 2 2
yes(1)
9S12XD256
112LQFP 80QFP 144LQFP
4 2 4 4 2 2 2 2 2 2 2 2
2 2 3 3 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1
8 8 8 8 8 8 8 8 8 8 8 8
4 4 4 4 4 4 4 4 4 4 4 2
3S12XDT256
112LQFP 80QFP 112LQFP
9S12XDG128
80QFP 112LQFP
3S12XDG128
80QFP 112LQFP
9S12XD128
2 1 1 1
80QFP
9S12XD64
80QFP
NOTES:
1. Can execute code only from RAM 2. ATD1 routed to PAD00-15 instead of PAD08-23.
MC9S12XD Family, Rev. 2.14 12 Freescale Semiconductor
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MC9S12XD Family Block Diagram
Pinout explanations: * * A/D is the number of modules/total number of A/D channels. I/O is the sum of ports capable to act as digital input or output. - 144 Pin Packages: Port A = 8, B = 8, C=8, D=8, E = 6 + 2 input only, H = 8, J = 7, K = 8, M = 8, P = 8, S = 8, T = 8, PAD = 24 25 inputs provide Interrupt capability (H =8, P= 8, J = 7, IRQ, XIRQ) 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) 80 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ)
-
-
* * * * * * * * * * * * * * *
CAN0 can be routed under software control from PM[1:0] to pins PM[3:2] or PM[5:4] or PJ[7:6]. CAN4 pins are shared between IIC0 pins. CAN4 can be routed under software control from PJ[7:6] to pins PM[5:4] or PM[7:6]. Versions with 5 CAN modules will have CAN0, CAN1, CAN2, CAN3 and CAN4 Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4 Versions with 3 CAN modules will have CAN0, CAN1 and CAN4. Versions with 2 CAN modules will have CAN0 and CAN4. Versions with 1 CAN modules will have CAN0 Versions with 2 SPI modules will have SPI0 and SPI1. Versions with 4 SCI modules will have SCI0, SCI1, SCI2 and SCI4. Versions with 2 SCI modules will have SCI0 and SCI1. Versions with 1 IIC module will have IIC0. SPI0 can be routed to either Ports PS[7:4] or PM[5:2]. SPI1 pins are shared with PWM[3:0]; In 144 and 112-pin versions, SPI1 can be routed under software control to PH[3:0]. SPI2 pins are shared with PWM[7:4]; In 144 and 112-pin versions, SPI2 can be routed under software control to PH[7:4]. In 80-pin packages, SS-signal of SPI2 is not bonded out!
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MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 13
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Pin Assignments
Pin Assignments
Table 3. Port and Peripheral Availability by Package Option
Port Port AD/ADC Channels Port A pins Port B pins Port C pins Port D pins Port E pins incl. IRQ/XIRQ input only Port H pins Port J pins Port K pins Port M pins Port P pins Port S pins Port T pins Sum of Ports VDDX/VSSX 144 LQFP 24/24 8 8 8 8 8 8 7 8 8 8 8 8 119 4/4 112 LQFP 16/16 8 8 0 0 8 8 4 7 8 8 8 8 91 3/3 80 QFP 8/8 8 8 0 0 8 0 2 0 6 7 4 8 59 2/2
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Table 4. Peripheral-Port Cross Reference(1)
CAN0 CAN1 CAN2 CAN3 CAN4 SCI0 SCI1 SCI2 SCI3 SCI4 SCI5 SPI0 SPI1 SPI2 IIC0 X
PJ1:0 PJ3:2 PJ5:4 PJ7:6 PM1:0 PM3:2 PM5:4 PM7:6 PS1:0 PS3:2 PS7:4 PH3:0 O X O O X X X O X X X
X
O O X
X O
MC9S12XD Family, Rev. 2.14 14 Freescale Semiconductor
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IIC1 X
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Pin Assignments
Table 4. Peripheral-Port Cross Reference(1)
CAN0 CAN1 CAN2 CAN3 CAN4 SCI0 SCI1 SCI2 SCI3 SCI4 SCI5 SPI0 SPI1 SPI2 IIC0 IIC1 5th Function
PH5:4 PH7:6 PP3:0 PP7:4 NOTES:
X X X
O O
X
1. X denotes the reset condition and O denotes a possible rerouting under software control
Table 5. Pin-Out Summary(1) LQFP 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 6 7 8 9 10 11 12 13 14 LQFP 112 1 2 3 4 QFP 80 1 2 3 4 Pin PP3 PP2 PP1 PP0 PJ2 2nd Function KWP3 KWP2 KWP1 KWP0 KWJ2 3rd Function PWM3 PWM2 PWM1 PWM0 CS1 4th Function SS1 SCK1 MOSI1 MISO1
PK6 ADDR22 NOACC www..com PK3 ADDR19 PK2 PK1 PK0 PT0 PT1 PT2 PT3 VDD1 VSS1 PT4 PT5 PT6 PT7 PK5 PK4 PJ1 PJ0 IOC4 IOC5 IOC6 IOC7 ADDR21 ADDR20 KWJ1 KWJ0 TXD2 RXD2 ADDR18 ADDR17 ADDR16 IOC0 IOC1 IOC2 IOC3 IQSTAT2 IQSTAT1 IQSTAT0
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 15
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Pin Assignments
Table 5. Pin-Out Summary(1) LQFP 144 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 24 25 26 27 28 29 30 31 32 33 34 35 36 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 LQFP 112 23 QFP 80 15 Pin BKGD VDDX2 VSSX2 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC4 PC5 DATA8 DATA9 DATA10 DATA11 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 DATA12 DATA13 UDS 2nd Function MODC 3rd Function 4th Function 5th Function
PC6 DATA14 www..com PC7 DATA15 PH7 PH6 PH5 PH4 PE7 PE6 PE5 PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PH3 KWH3 SS1 TXD7 KWH7 KWH6 KWH5 KWH4 XCLKS MODB MODA ECLK SS2 SCK2 MOSI2 MISO2 ECLKX2 TAGHI TAGLO RE TXD5 RXD5 TXD4 RXD4
MC9S12XD Family, Rev. 2.14 16 Freescale Semiconductor
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Pin Assignments
Table 5. Pin-Out Summary(1) LQFP 144 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 65 66 67 68 69 70 71 72 73 74 75 76 55 54 53 52 49 50 51 53 54 55 56 57 58 59 60 61 62 63 64 37 38 39 40 41 42 43 44 45 46 LQFP 112 50 51 52 QFP 80 Pin PH2 PH1 PH0 PD0 PD1 PD2 PD3 PE3 PE2 PE1 PE0 PA0 PA1 PA2 PA3 PA4 PA5 2nd Function KWH2 KWH1 KWH0 DATA0 DATA1 DATA2 DATA3 LSTRB RW IRQ XIRQ ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 LDS WE EROMCTL 3rd Function SCK1 MOSI1 MISO1 4th Function RXD7 TXD6 RXD6 5th Function
47 PA6 ADDR14 www..com 48 PA7 ADDR15 VDDX3 VDDX3 PD4 PD5 PD6 PD7 VDD2 VSS2 PAD00 PAD08 PAD01 PAD09 PAD02 PAD10 PAD03 PAD11 PAD04 PAD12 AN0 AN8 AN1 AN9 AN2 AN8 AN3 AN11 AN4 AN12 DATA4 DATA5 DATA6 DATA7
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 17
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Pin Assignments
Table 5. Pin-Out Summary(1) LQFP 144 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 100 101 102 103 70 71 72 73 87 88 89 90 91 92 93 94 95 96 97 98 99 67 68 69 63 64 65 66 83 84 85 86 59 60 61 62 LQFP 112 77 78 79 80 81 82 58 57 QFP 80 56 Pin PAD05 PAD13 PAD06 PAD14 PAD07 PAD15 PAD16 PAD17 VDDA VRH VRL VSSA PAD18 PAD19 PAD20 PAD21 PAD22 AN18 AN19 AN20 AN21 AN22 2nd Function AN5 AN13 AN6 AN14 AN7 AN15 AN16 AN17 3rd Function 4th Function 5th Function
PAD23 AN23 www..com PM7 TXCAN3 TXCAN4 TXD3 PM6 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 VREGEN PJ7 PJ6 PJ5 PJ4 PM5 PM4 PM3 PM2 KWJ7 KWJ6 KWJ5 KWJ4 TXCAN2 RXCAN2 TXCAN1 RXCAN1 TXCAN4 RXCAN4 SCL1 SDA1 TXCAN0 RXCAN0 TXCAN0 RXCAN0 SCL0 SDA0 CS2 CS0 TXCAN4 RXCAN4 SS0 MISO0 SCK0 MOSI0 RXCAN3 RXD0 TXD0 RXD1 TXD1 MISO0 MOSI0 SCK0 SS0 RXCAN4 RXD3
MC9S12XD Family, Rev. 2.14 18 Freescale Semiconductor
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Pin Assignments
Table 5. Pin-Out Summary(1) LQFP 144 136 137 138 139 140 141 142 143 144 LQFP 112 104 105 106 107 108 109 110 111 112 79 80 78 QFP 80 74 75 76 77 Pin PM1 PM0 VSSX1 VDDX1 PK7 PP7 PP6 PP5 PP4 ROMCTL KWP7 KWP6 KWP5 KWP4 EWAIT PWM7 PWM6 PWM5 PWM4 SCK2 SS2 MOSI2 MISO2 2nd Function TXCAN0 RXCAN0 3rd Function 4th Function 5th Function
NOTES: 1. Table shows a superset of pin functions. Not all functions are available on all derivatives
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MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 19
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Pin Assignments
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0 PJ7/KWJ7/TXCAN4/SCL0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 PAD23/AN23 PAD22/AN22 PAD21/AN21 PAD20/AN20 PAD19/AN19 PAD18/AN18 VSSA VRL
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 CS1/KWJ2/PJ2 NOACC/ADDR22/PK6 ADDR19/PK3 IQSTAT2/ADDR18/PK2 IQSTAT1/ADDR17/PK1 IQSTAT0/ADDR16/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 ADDR21/PK5 ADDR20/PK4 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD VDDX2 VSSX2 DATA8/PC0 DATA9/PC1 DATA10/PC2 DATA11/PC3 UDS/ADDR0/PB0 ADDR1/PB1 ADDR2/PB2 ADDR3/PB3 ADDR4/PB4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
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Pins shown in BOLD-ITALICS are bit available on the 112 LQFP nor on the 80 QFP Package Option
MC9S12XD Family 144 LQFP
Pins shown in BOLD are not available on the 80 QFP package
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VRH VDDA PAD17/AN17 PAD16/AN16 PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PD7/DATA7 PD6/DATA6 PD5/DATA5 PD4/DATA4 VDDX3 VSSX3 PA7/ADDR15 PA6/ADDR14 PA5/ADDR13 PA4/ADDR12 PA3/ADDR11 PA2/ADDR10 PA1/ADDR9 PA0/ADDR8
Figure 1. MC9S12XD Family Pin Assignments for 144-pin LQFP Package
MC9S12XD Family, Rev. 2.14 20 Freescale Semiconductor
ADDR5/PB5 ADDR6/PB6 ADDR7/PB7 DATA12/PC4 DATA13/PC5 DATA14/PC6 DATA15/PC7 TXD5/SS2/KWH7/PH7 RXD5/SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 XCLKS/ECLK2X/PE7 TAGHI/MODB/PE6 RE/TAGLO/MODA/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PD0/DATA0 PD1/DATA1 PD2/DATA2 PD3/DATA3 EROMCTL/LDS/LSTRB/PE3 WE/RW/PE2 IRQ/PE1 XIRQ/PE0
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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Pin Assignments
Figure 2. MC9S12XD Family Pin Assignments for 112-pin LQFP Package
Freescale Semiconductor
PB5 PB6 PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 TXD4/MOSI2/KWH5/PH5 RXD4/MISO2/KWH4/PH4 ECLK2X/XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 PE3 PE2 IRQ/PE1 XIRQ/PE0
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 PK3 PK2 PK1 PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 PK5 PK4 TXD2/KWJ1/PJ1 RXD2/KWJ0/PJ0 MODC/BKGD PB0 PB1 PB2 PB3 PB4
112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7 VDDX VSSX PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0 PJ7/KWJ7/TXCAN4/SCL0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4/RXD3 PM7/TXCAN3/TXCAN4/TXD3 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MC9S12XD Family 112LQFP
Pins shown in BOLD are not available on the 80 QFP package
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VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
MC9S12XD Family, Rev. 2.14 21
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Pin Assignments
PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA0/RXCAN0 PJ7/KWJ7/TXCAN4/SCL0/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MC9S12XD Family 80-Pin QFP
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PB5 PB6 PB7 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Figure 3. MC9S12XD Family Pin Assignments for 80-pin QFP Package
MC9S12XD Family, Rev. 2.14 22 Freescale Semiconductor
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Memory Maps
Memory Maps
$0000 2K Register Space $0800 $0C00 $1000 4K Bytes EEPROM 4 * 1K pages accessible through $0800 - $0BFF
$2000 32K Bytes RAM 8 * 4K pages accessible through $1000 - $1FFF
$4000
16K Fixed Flash EEPROM
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$8000 External 16K Page Window 32 * 16K Flash EEPROM Pages
$C000
16K Fixed Flash EEPROM
$FF00 VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED BDM SPECIAL SINGLE CHIP $FFFF
2K, 4K, 8K or 16K Protected Boot Sector
Figure 4. MC9S12XD-Family Memory Map1
1. The memory Map shows the memory sizes of DP512 part. For memory configuration of other parts see Table 1. MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 23
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Memory Maps
Global Address $78_0000 (PPAGE $E0)
DP512/ DT512
DT384
DQ256/ D256
DG128/ D128
D64
128K
$7A_0000 (PPAGE $E8)
128K
128K
128K
$7C_0000 (PPAGE $F0)
128K
$7E_0000 (PPAGE $F8)
128K
128K
128K
128K
128K
64K
Shared XGATE/CPU area Not implemented
Figure 5. MC9S12XD-Family Flash Configuration1, 2, 3, 4, 5
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1. XGATE read access to Flash not possible on DG128/D128 and D64 2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF 3. Program Pages available on DQ256/D256 are $E0 - $E7 and $F8 - $FF 4. Shared XGATE/CPU area on DP512/DT512/DT384 at global address $78_0800 to $78_FFFF (30Kbyte) 5. Shared XGATE/CPU area on DQ256/D256 at global address $78_0800 to $79_3FFF (46Kbyte) MC9S12XD Family, Rev. 2.14 24 Freescale Semiconductor
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Mechanical Package Dimensions
Mechanical Package Dimensions
4X
0.20 T L-M N
4X 36 TIPS
0.20 T L-M N
PIN 1 IDENT 1
144
109
108
J1 J1 L M B V
140X
4X
P
C L X G
VIEW Y
36 73
B1
V1
VIEW Y
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35.
37
72
N A1 S1 A S
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VIEW AB 2 2 T 0.1 T
144X SEATING PLANE
C
PLATING
J
F
AA
C2 0.05 R2 R1
D 0.08
M
BASE METAL
0.25
GAGE PLANE
T L-M N (K) C1 (Y) VIEW AB (Z) E 1
SECTION J1-J1 (ROTATED 90 )
144 PL
MILLIMETERS DIM MIN MAX A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0.16 0 1 0 7 2 11 13
Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03)
MC9S12XD Family, Rev. 2.14 Freescale Semiconductor 25
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Mechanical Package Dimensions
4X PIN 1 DENT 1 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE
C2 C 0.050
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VIEW AB 2 0.10 T
112X SEATING PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13
3 T
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
Figure 7. 112-pin LQFP Mechanical Dimensions (case no. 987)
MC9S12XD Family, Rev. 2.14 26 Freescale Semiconductor
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60 61
41 40
S
S
B B P
D
S
-AL
-BB
0.20 M H A-B
V 0.05 D
0.20 M C A-B
S
D
-A-,-B-,-DDETAIL A
DETAIL A
80 1 20
21
-DA 0.20 M H A-B 0.05 A-B S 0.20 M C A-B
S S
F
D
S
J D
S
N
E C -CSEATING PLANE
M DETAIL C
D 0.20 M C A-B SECTION B-B
S
D
S
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-HDATUM PLANE
VIEW ROTATED 90
H G
0.10
M
U T
DATUM -HPLANE
R
K W X DETAIL C
Q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N P Q R S T U V W X
MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF
Figure 8. 80-pin QFP Mechanical Dimensions (case no. 841B)
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9S12XDFAMPP Rev. 2.14, 7-Nov-2005
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